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wireless power receiver for 3w applications p9027lp - r datasheet ? 2016 integrated device technology, inc 1 april 28, 2016 description the p9027lp - r is a highly integrated, low bill - of - m aterials (bom) count, single - chip receiver targeted for 0 .5 to 3 w applications. using the magnetic inductive charging technology, i t convert s an ac power signal from a resonant tank into a reg ulated programmable dc output voltage ranging from 4.5 to 6.0 volts. the receiver has a patented internal scheme for communication and m odulation using zero external components. as a result, it provides an extremely small application area. together with t he p9235a - r transmitter, the p9027lp - r is a complete wireless power system solution. the p9027lp - r is available in a wlcsp - 40 package (2.24 mm 3.62 mm, 0.4 mm pitch), and it is rated for 0 to 85c ambient operating temperature range . typical applications ? smart watches ? headsets ? digital cameras ? portable medical a pplications figure 1 . typical applications circuit features ? s mall s olution a rea : ~ 3 2 mm 2 ? patented over - voltage protection clamp eliminating external capacitors ? optimized for 0 .5 to 3 w applications ? integrated low dropout tracking ldo ? low synchronou s rectifier r ds(on) for high efficiency ? programmable rectifier voltage for optimal transient response versus efficiency ? integrated charge pump for startup under weak coupling or poor alignment ? programmable o utput v oltage : 4.5 to 6.0 v ? programmable current limit ? open - drain interrupt flag ? power transfer led indicator ? dedicated remote temperature sensing ? active low enable pin for electrical on/off ? i 2 c interface ? 0 to +85c ambient operating temperature range ? wlcsp 2.24 mm x 3.62 mm, 40 pin package p 9 0 2 7 l p - r l x 1 v r e c t c r e c t r 1 a g n d s c l s d a s c l s d a c d o u t c o u t v o u t = 5 v c h i p e n a b l e c f l y c f l y 1 p g n d v h d r v s e t e n d o f c h a r g e l r x i n t e r u p t e o c o u t s n s c f l y 2 l x 2 v d d c v d d t s 1 t s 2 r t s 1 r t s 2 i n t e n r h d r i o c r i o c a c t
p9027lp - r datasheet ? 2016 integrated device technology, inc 2 april 28, 2016 ab solute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 1 . thermal information 1,2 pins rating units rect, out, outsns - 0.3 t o 9.0 v lx1, lx2 - 0.8 to 9.0 v pgnd , agnd - 0.3 to 0.3 v vdd, cfly1, cfly2, sda, scl, en ? ? ? ? , act ? ? ? ? ? ? , ioc, vset, vhdr, int ? ? ? ? ? , eoc, ts1, ts2, - 0.3 to 6.0 v maximum input current into sfbr 3.0 a all voltages here are measured with respect to analog ground p in (agnd). table 2 . thermal symbol information 1,2 symbol description rating units ? ja thermal resistance (wlcsp - 40) 71 ? c/w ? j c thermal resistance junction to case 18 ? c/w t a ambient operating temperature range 0 to 85 ? c t j ju nction operating temperature range 0 to 125 ? c t js junction storage temperature range - 55 to 150 ? c t lead maximum soldering temperature (at leads) 300 ? c notes: 1. the maximum power dissipation is p d(max) = (t j(max ) - t a )/ ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 2. the thermal rating was calculated based on a jedec 51 standard 4 - layer board, 6 vias with dimensions 4 in 4.5 in still air conditions. actual thermal resistance will be affected by pcb size, solder joint quality, pcb layer count, copper thickness, air flow, altitude, and other unlisted variables. table 3 . esd informat ion test m odel pins rating units hbm all 2,000 v cdm all 500 v
p9027lp - r datasheet ? 2016 integrated device technology, inc 3 april 28, 2016 electrical specification table v rect = 6.5 v , c out =c vrect =20 f, c fly =47 nf, c vdd =1 f, en ? ? ? ? =gnd, v out =5 v, t a = 0 to +85c, unless otherwise noted. typic al values are 25c. table 4 . electrical specification table symbol description conditions min typ ical max units synchronous full bridge rectifier (sfbr) v lx voltage across sfbr 0.0 7 .0 v r on - hs high - side r ds_on forward current = 0.7 - 1.0 a, t a =25 o c 45 m? r on - l s low - side r ds_on forward current = 0.2 - 0.5 a, t a =25 o c 30 m? v clamp internal clamping voltage rectifier clamp (hardwired) 7.4 v charge pump 2 vdd charge pump output voltage i vdd = 0 C 5 ma; v rect = 3 - 8 v 4.0 5.0 5.5 v v rect_min minimum v rect i vd d = 5 ma 1.9 v i rect bias current v rect = 5 v 5.0 8.0 ma v rect = 3 v 8.0 uvlo rise rising voltage of uvlo 2.7 3.0 3.4 v uvlo hyst hysteresis of uvlo 0.4 v output current i out output current range v out = 5.0v 0 600 ma i out_leak leakage c ur rent no transmitter present ; v out =5v 30 60 a i out_res output current resolution adc resolution 0.5 ma fsr error 1 v out = 5.0 v, i out = 0. 2 C 0. 5 a 0.2 8.2 % fsr v out = 5.0 v, i out = 0. 2 C 0. 5 a, t a = 25 o c 0.2 4.4 programmable ldo v out output voltage range 4.5 5.0 6.0 v v accu output voltage a ccuracy v out = 3.0 C 5.0v, i out = 0 2.3 % v out = 3.0 C 5.0v, t a = 25 o c 0.6 v drop dropout voltage i out = 500ma 25 mv
p9027lp - r datasheet ? 2016 integrated device technology, inc 4 april 28, 2016 electrical specification table ( continued ) v rect =6.5 v, c out =c vrect =20 f, c fly =47 nf, c vdd =1 f, en ? ? ? ? =gnd, v out =5 v, t a = 0 to +85c, unless otherwise noted. typical values are 25c . table 4 . electrical specification table (continued) symbol description conditions min typ ical max units 12 - bit a nalog to digital converter v ref reference voltage 1.8 v fsr error 1 vdd = 5.0 v 0.1 2.3 % fsr v dd = 5.0 v, t a = 25 o c 0.1 0.6 f sample sampling rate 60 ks/s vhdr, vset, ts1, ts2 , ioc i src source current vdd = 3.0 - 5.5 v 98 100 102 a v rsn s sense voltage 0 1.8 v r set resistor range 1% tolerance 0 18 k digital inputs and outputs (scl, sda, en ? ? ? ? int ? ? ? ? ? act ? ? ? ? ? ? v ol open drain: int ? ? ? ? ? act ? ? ? ? ? ? sink = 4 ma 0.4 v v ih input logic high voltage 1.0 v v il input logic low voltage 0.4 v i 2 c interface v ih input high voltage scl, sda 1.1 v v il input low voltage scl, sda 0.4 v f scl clock frequency 400 khz c b capacitive load 150 pf c bin scl, sda input capacitance 5 pf t hd,sta hold time (repeated) for start conditio n 0.6 s t hd:dat data hold time 0 ns t low clock low period 1.3 s t high clock high period 0.6 s
p9027lp - r datasheet ? 2016 integrated device technology, inc 5 april 28, 2016 electrical specification table ( continued ) v rect =6.5 v, c out =c vrect =20 f, c fly =47 nf, c vdd =1 f, en ? ? ? ? =gnd, v out =5 v, t a = 0 to +85c, unless o therwise noted. typical values are 25c . table 4 . electrical specification table (continued) symbol description conditions min typical max units 12 - bit an alog to digital converter t su:sta set - up time for repeated start condition 0.6 s t buf bus free time between stop and start condition 1.3 s thermal shutdown 1 t shd thermal shutdown 1 3 0 o c t shd - hys thermal shutdown hysteresis 20 o c notes: 1. guaranteed by design and not subject to 100% production testing. 2. do not externally load. for internally biasing only.
p9027lp - r datasheet ? 2016 integrated device technology, inc 6 april 28, 2016 typical p erformance c haracteristics figure 2 . typical performance characteristics C 3w figure 3 . typical performance characteristics C 2w figure 4 . typical performance characteristics C 1w -0.5 -0.3 -0.1 0.1 0.3 0.5 0 40 80 120 160 200 240 280 320 360 400 loasd regulation (%) iout (ma) load regulation - 2w vin=5v, vout=5v, tx=p9235a - r, gap=1.5mm tx coil=760308101104, rx coil=760308101220 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 60 120 180 240 300 360 420 480 540 600 efficiency (%) iout (ma) efficiency vs. output load current - 3w vin=5v, vout=5v, iout=600ma, tx=p9235a - r, gap=1.5mm tx coil=760308101103, rx coil=760308102213 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 60 120 180 240 300 360 420 480 540 600 loasd regulation (%) iout (ma) load regulation - 3w vin=5v, vout=5v, iout=600ma, tx=p9235a - r, gap= 1.5mm tx coil=760308101103, rx coil=760308102213 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 40 80 120 160 200 240 280 320 360 400 efficiency (%) iout (ma) efficiency vs. output load current - 2w vin=5v, vout=5v, tx=p9235a - r, gap=1.5mm tx coil=760308101104, rx coil=760308101220, 0.00 10.00 20.00 30.00 40.00 50.00 60.00 20 40 60 80 100 120 140 160 180 200 efficiency (%) iout (ma) efficiency vs. output current - 1w vin=5v, vout=5v, iout=200ma, tx=p9235a - r, gap=1.5mm tx coil=wt151512 - 21f2, rx coil=wr121220 - 27m8 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 20 40 60 80 100 120 140 160 180 200 loasd regulation (%) iout (ma) load regulation - 1w vin=5v, vout=5v, iout=200ma, tx=p9235a - r, gap= 1.5mm tx coil=wt151512 - 21f2, rx coil=wr121220 - 27m8
p9027lp - r da tasheet ? 2016 integrated device t echnology, inc 7 april 28, 2016 figure 5 . ebn and enb ept figure 6 . vin_start_up_600ma_1 and enb_startup_600ma_1 enb_startup_600ma_1 figure 7 . eoc and oc1
p9027lp - r da tasheet ? 2016 integrated device t echnology, inc 8 april 28, 2016 figure 8 . tsi and ts1 ept ts1 ept
p9027lp - r da tasheet ? 2016 integrated device t echnology, inc 9 april 28, 2016 pin configuration figure 9 . pin configuration a b c d e f g p g n d 5 4 3 2 1 p g n d p g n d p g n d p g n d p g n d l x 1 r e c t r e c t r e c t r e c t r e c t o u t s n s i o c n / c e o c v d d a g n d t s 1 a g n d s d a s c l h o u t b o t t o m v i e w l x 1 l x 2 l x 2 o u t o u t n / c c f l y 1 c f l y 2 n / c n c v s e t t s 2 e n a c t i n t r s v d v h d r
p9027lp - r da tasheet ? 2016 integrated device t echnology, inc 10 april 28, 2016 pin description table 5 . pin description pins name typical description pgnd a1, a2, a3, a4, a5, b3 gnd power ground . lx2 b1, b2 i connect the rx coil to this pin. lx1 b4, b5 i connect the other side of rx coil to this pin. rect c1, c2, c3, c4, c5 o output voltage of the synchronous rectifier bridge. connect at least two 10 f capacito rs from this pin to pgnd. the rectifier voltage dynamically changes as the load changes . see typical curves. cfly2 d1 o positive and negative terminals of the internal charge pump. connect a 47 nf capacitor between these two pins. cfly1 d2 o out d3, d4 , d5 o regulated output voltage pin. connect at least two 10 f capacitors from this pin to pgnd. the default voltage is set to 5v when vset is directly shorted to gnd . for more information s ee vset application section. nc e1, e2, e4, f2 nc do not connect . rsvd e3 i this pin is r eserved for internal use. connect a 1.69 k ? resistor from this pin to gnd for 1 w coil . for 2 w and 3 ws coils , use a 1.13 k? resistor . outsns e5 i feedback input pin. this pin must be connected directly to out pin to provide a regulated voltage. ioc f1 i programmable over - current limit pin. c onnect a resistor from this pin to gnd to set the current - limit threshold. to disable the current - limit, connect the pin directly to gnd. for more information s ee current limit application section. eoc f3 i active high end of charge input pin. when conne cted to logic high, the device sends end of power transfer packet (charge complete) to the transmit ter to terminate power transfer and shuts down . the out pin is high impedance after p9027lp - r is shutdown vset f4 i programming pin to set the output voltag e. connect a resistor from the pin to gnd to set the output voltage . shorting the pin to gnd sets the output voltage to 5 v. for more information r efer to the application section vset for different output voltage settings . vhdr f5 i programming pin to set the rectifier voltage. connect a resistor from the pin to ground. refer to the application section for appropriate resistor selection . vdd g1 o charge pumps regulated 5 v supply to power the internal circuitry. connect a 1 f capacitor as close as possib le from this pin to gnd. do not load the pin. en g2 i active low enable pin. pulling this pin to logic high forces the device into shutdown mode. when connected to logic low, the device is enabled. do not leave the pin floating. agnd g3, h1 gnd analog ground. ts2 g4 remote temperature sensor 2. if not used, connect to agnd.
p9027lp - r da tasheet ? 2016 integrated device t echnology, inc 11 april 28, 2016 table 5 . pin description (continued) pins name typical description ts1 g5 remote temperature sensor 1. if not used, connect to agnd. sda h2 i/o i 2 c data pin. open drain output. connect a 5.1 k resistor from this pin to vdd. scl h3 i i 2 c clock pin. open drain output. connect a 5.1 k resistor from this pin to vdd. int act
p9027lp - r datasheet ? 2016 integrated device technology, inc 12 april 28, 2016 functional block diagram figure 10 . functional block diagram
p9027lp - r datasheet ? 2016 integrated device technology, inc 13 april 28, 2016 description of the wireless power system i nductive wireless power transfer involves transmission of energy by changing the magne tic field from a power source to an electrical load, without any connector, across an air gap. the dc power applied to the transmitter (tx) creates an ac magnetic field in the transmitter coil. once the receiver (rx) coil is placed near the magnetic field , the field will induce an ac current through the r eceiving coil where it is converted into a dc current. the communication between receiver and the transmitter is accomplished by modulating the load seen by the receiver's inductor. to the transmitter, this appears as an impedance change, which results in measurable variations of the transmitters output waveform. modulation is accomplished with ac modulation, using internal switches from lx1 and lx2 to ground. the amount of power transferred is controlled b y the receiver. the receiver sends communication packets to the transmitter to increase power, decrease power, maintain the power level, or terminate the power transfer. the bit rate for rx - to - tx communication link is 2 kbps. the communication is digital a nd communication of 1's and 0's is achieved by the rx modulating the amount of load on the receiver coil. theory o f operation the p9027lp - r w ireless p ower r eceiver works according to the m agnetic i nduction (mi) principle. the tx and rx coils are coupled wi th a coupling factor between 0.1 and 0.9, and power is transferred through an ac magnetic field. the p9027lp - r is a highly - integrated w ireless p ower r eceiver with a maximum output power of 3 watts . it is designed to convert an ac power signal from a reson ant tank into a regulated output voltage. the device includes a high - efficiency sy nchronous full - bridge rectifier with ultra - low r ds(on) , nmos ldo, and a charge pump for quick startup under very weak coupling or poor coil alignment. the output voltage is p rogrammable w from 4.5 to 6.0 v . programming is accomplished with a single external resistor on the vset pin to ground. the receiver utilizes idts proprietary voltage clamping scheme which limits the maximum voltage at the rectifier pin to 9 v, reducing the voltage rating on the output capacitors while eliminating the need for ovp and communication capacitors. as a result, it provides an extremely small application area , mak ing it an industry - leading wireless power receiver for high power density applicat ions . together with p9235a - r transmitter, the p9027lp - r is a complete wireless power system solution . the end of charge (eoc) pin is a logic input , which can be used with application processor or charger ic in battery management applications . when asserted , it sends an end of charge packet to the transmitter , terminating the power transfer and shutting down the device. the electrical on/off of the device is controlled through en ? ? ? ? pin. when connected to logic high, the device shuts down and consumes minimum current. communication between the p9027lp - r and p9235a - r when the p902 7lp - r is placed on p9235a - r tx coil , it responds to the transmitter's "ping" signal by rectifying the ac power from the transmitter and storing it on capacitor s connected to v rect . dur ing the "ping" phase, the rectifier provides voltage to the charge pump to supply vdd, and thus , power up the internal control circuitry and logic inside the receiver . to increase the reliability of communication, an internal load of approximately 20 ma is connected to vrect until the external load is large enough to support communication. during power up, t he p9027lp - r communicates signal strength, identification and configuration packets to the transmitter , respectively. once the handshake between rx and tx has been established, the wireless power system is in the power transfer phase . the control loop of the p9027lp - r then adjusts the rectifier voltage (based on load condition) by sending control error packets instruction to the transmitter. during power de livery to the load, the p9027lp - r control circuit continues to send control error packets to the transmitter to adjust the operating frequency, and thus rectifier voltage , to the level required to maximize the efficiency of the linear regulator. over - vol tage protection one of the common issues with wireless power receivers is the potential that the transmitter (tx) will transmit more power th an the receiver needs or can handle. this can happen when the coupling between the tx and rx increases due to a sud den move of the receiver. because of the slow communication, it may take up to a few seconds before the tx can adapt its transmitting power, and this may be long enough for the voltage on the lx and rect pins to increase above the maximum ratings and damag e the receiver. for this reason, the p9027lp - r has over - voltage protection. in most wireless receiver chips, this is implemented by external clamping capacitors. however, the p9027lp - r has implemented this feature internally to save board space and reduce the bom cost. furthermore, since the clamping is activated around 8.5 v, the bulk capacitors can have a low voltage rating.
p9027lp - r datasheet ? 2016 integrated device technology, inc 14 april 28, 2016 charge pump for internal power supply - vdd the power supply for the control circuitry in the p9027lp - r is generated by a charge pu mp. this charge pump requires a 0.47 f flying capacitor connected between the cfly1 and cfly2 terminals . a 1 f capacitor with a recommended voltage rating of 25 v must be connected from vdd to gnd . adding any external loads to this pin is prohibited as t h e charge pump output current is limited to 5 ma. rectifier voltage headroom setting C vhdr the rectifier voltage dynamically changes as a function of load when the vhdr resistor is fixed. the reason is to balance power dissipation and dynamic load respons e . under the condition of a step load, the wireless power system may not have enough power to respond. this is due to the communication of the rx - to - tx feedback loop being relatively slow C where it can take up to several tens of milliseconds for the power required b y the receiver to be delivered. thus, a higher rectifier voltage is preferred to mitigate the step load transient response. o n the other hand, a high rectifier voltage will generate more power loss on the ldo. thus, to meet the requirements of b oth power dissipation and transient response, the rectifier voltage typically starts at around 6.5v at no load , and it is adjusted to the appropriate value base d on the output load once the communication is complete. figure 11 shows how the rectifier volta ge changes with load . t he rectifier voltage is set by connecting a 1% resistor from the vhdr pin to gnd. the table below recommends the appropriate resistor value based on system efficiency and transient response when using p9235a - r and p9027lp - r . table 6 . resistor value and output current resistor value ( k? ) output current 1.13 0 C 400ma 1.69 400 C 600ma rectifier voltage - rect the rectifier output ( rect pin) requires at least a 20 f ceramic capacitor from the pin to gnd to minimize the ripple voltage. it is recommended to use at le ast either two 10 f or four 4.7 f capacitors to reduce the total capacitor esr. when selecting a ceramic capacitor, only x5r and x7r dielectric types should be used. other types such as z5u and y5f have su ch severe loss of capacitance due to effects of temperature variation and applied voltage, they may provide as little as 20% of rated capacitance in many typical applications. always consult the capacitor manufacturers data curves before selecting a capacitor. setting the output v oltage - vset the p902 7lp - r output voltage can be programmed from 4.5 to 6.0 v by connecting a resistor from the vset pin to gnd x allowing selection from pre - programmed voltages. see the table below for the desired output voltage with an appropriate resistor value. table 7 . resistor value and output voltag e resistor value ( k? ) output voltage 3.40 4.50 4.22 4.75 gnd 5.00 5.36 5.25 6.49 5.50 7.68 5.75 9.09 6.00 over - current limit C ioc the output over - current (oc) protection mechanism relies o n the comparison between the sensed current and the programmed over - current threshold. the over - current threshold is set through a single external resistor , connected between the ioc pin and gnd . a pulse 100 a of current is sourced from the ioc pin to gnd . if ioc pin is shorted to gnd, t he protection is disabled . the ldo output current sensing is
p9027lp - r datasheet ? 2016 integrated device technology, inc 15 april 28, 2016 accomplished internally through sensing circuitry and then digitized by adc . the current sensing does not vary with the temperature. r efer to the electrical chara cteristic table for current sense accuracy . the internal current sensing accuracy degrades during light - load conditions. when the over - current limit is tripped , the p9027lp - r send s end of power transfer over - current packet (ept: oc) to the p9235a - r , shutt ing down the entire system. in the event th e transmitter fail s to recognize the packet , the receiver will continue sending the ept: oc packet up to 12 times. the oc limit is typically set to ~24% higher than maximum load. please refer to table 8 below for different current protection thresholds. table 8 . resistor value, over - c urrent setting resistor ( k? ) ioc limit max . output current gnd disabled - 2.26 260ma 200ma 6.19 5 4 0ma 400ma 9.53 780ma 600ma enable pin - ?? the enable pin ( en ) is an active low logic . when connected to logic high, the receiver shuts down by sending an end of power transfer (ept) packet to p9235a - r and forces the out pin to high impedance state. when connected to a log ic low, the device operates in normal mode. active flag pin - ??? the act pin is an open drain output indicator. connect a led from this pin to out to indicate connection between the receiver and the transmitter has been established and the power is being transferred. interrupt pin - ??? the p9027lp - r provides an open - drain, active low interrupt output pin . it is asserted high when en is high, eoc is logic high, die temperature reaches 130c, ts1 or ts2 and thermal shutdown have been triggered . during normal operation, the int pin is pulled high . this pin can be connected to the interrupt input of a microcontroller. the source of what triggered the interrupt is available in i2 c register. end of charge - eoc the end of charge feature is a ded icated pin that forces the p9235a - r to terminate power transfer when the eoc is logic high. when eoc is asserted, the device issues an end power transfer (ept) packet to the transmitter terminating all activities by placing p9235 a - r into standby mode. the p9235a - r will start digital ping after five minutes or if the p9027lp - r is removed. remote temperature sensing the p9027lp has two temperature sensor inputs, ts1 and ts2 that can be used to monitor two remote locations such as the battery and the rx coil. it is recommended to use an ntc thermistor typical 10 k , depending on the temperature range of interest (0 k C 18 k ) . the basic characteristic of an ntc thermistor is given below for reference. where: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 t 1 t 1 b exp r r
p9027lp - r datasheet ? 2016 integrated device technology, inc 16 april 28, 2016 t is the temperature in kelvin. r 0 is the known resistance at calibration temperat ure t 0 . b (beta) is the material constant. the adc reading of thermistors ts1 and ts2 can be monitored by the i 2 c interface . t he adc value can be calculated using the thermistor resistance formula and the following: recommended co ils the following coils are recommended with p9027lp - r receiver for 1 , 2 and 3 w applications for optimum performance . the recommended vendors have been tested and verified. table 9 . coils recommended with receiver for 1, 2 and 3 w applications. output power vendor part n umber inductance dcr dimension 1 w tdk wr121220 - 27m8 - id 8.32 uh 0.98 ? ?12 mm sunlord swa12r12h08c01b 8.50 uh 0.38 ? ?12 mm 2 w tdk wr202010 - 18m8 - id3 11.0 h 0. 40 ? ?20 mm w urth electronics 760308101220 12.60 h 0.27 ? ?17 mm sunlord swa20r20h08c01b 12.0 h 0.29 ? 20 mm x 20 mm 3 w tdk wr303050 - 12f5 - id1 8.20 h 0.30 ? 30 mm x 30 mm wurth electronics 760308102213 7.90 h 0.26 ? 29 mm x 29 mm sunlord swa30r30h08c01b 8.2 0 uh 0.33 ? 30 mm x 30 mm pcb layout consideration for optimum device performance and lowest output phase noise, idt recommends that customers copy the reference layout used in the p9027lp - r - evk reference kit. more information and layout files can be foun d at http://www.idt.com/wp3w - rk . additional layout guidelines can be found in application note an - 933 . users are encouraged to read this document prior to starting a board design. 255 1.8v a 10 100 r adc -6 ts ? ? ? ?
p9027lp - r datasheet ? 2016 integrated device technology, inc 17 april 28, 2016 reference schematic (p9027lp - r - evk) figure 11 . p9027lp - r mass market ev schematics
p9027lp - r datasheet ? 2016 integrated device technology, inc 18 april 28, 2016 component selection s table 10 . component selections item qty reference description pcb footprint mfg part number 1 4 c1, c2, c6, c7 cap 10 uf/10 v 402 cl05a106mp5nunc 2 2 c5, c8 res 0.0 ohm 402 erj - 2ge0r00x 3 1 c4 cap 1 uf/25 v 402 c1005x5r1e105m050bc 4 1 c3 cap 0.047 uf/25 v 402 c1005x7r1e473m050bc 5 1 c9 cap 1800 pf/50 v 402 grm155r71h182ka01d 6 2 r1, r2 res 5.11 k 201 erj - 1gef5111c 7 1 r3 res 6 80 402 erj - 2gej681x 8 1 r4 res 5.1 k 402 erj - 2gej512x 9 2 r5, r9 res 0.0 ohm 201 erj - 1ge0r00c 10 2 r6, r7 res 4.99 k 201 erj - 1gef4991c 11 1 r8 res 1.13 k 201 erj - 1gef1131c 12 1 r10 res 7.87 k 201 erj - 1gef7871c 13 2 r11, r15 res 2.49 k 402 erj - 2rkf249 1x 14 1 r12 res 1.69 k 201 erj - 1gef1691c 15 2 r13, r14 potential meter 10 k 2.2 mm x 2.1 mmx 0.8 mm pva2a103a01r00 16 1 d1 led indicator 402 led red 0402 smd 17 1 u1 wireless power rx ic 2.24 x 3.62 mm wlcsp, 0.4 mm pitch size p9027lp - r 18 1 l1 rx coi l see table 9
p9027lp - r datasheet ? 2016 integrated device technology, inc 19 april 28, 2016 i 2 c register map the default i 2 c slave address is 0x68. the intent of this register is to identify the device is p9027lp - r. table 11 . device identification byte address byte name bit f ield typical default value description 0xf c part_number_ h 7:0 r/w 0x 90 high byte of part number 0xfd part_number_l 7:0 r/w 0x 27 low byte of device naming code this register will provides information about firmware version programmed into the ic. table 12 . firmware version id byte address byte name bit field typical default value description 0xff chip_id_l 7:0 r 0xab firmware version all the faults can cause p 9027lp - r send ept (end of power t ransfer) package with different valu es or pull int pin high. the faults can be enabled by setting masked f ault enable register. bit of flt_raw will be set if co r re s ponding fault condition is trigged. table 13 . masked fault enable register byte address byte name bit f ield typical default value description 0xd4 flt_raw_15 7 r 0 reserved. 0xd4 flt_raw_14 6 r 0 reserved. 0xd4 flt_raw_13 5 r 0 reserved 0xd4 flt_raw_12 4 r 0 reserved. 0xd4 flt_raw_11 3 r 0 reserved 0xd4 flt_raw_10 2 r 0 reserved. 0xd4 flt_raw_9 1 r 0 reserved 0xd4 flt_raw_8 0 r 0 reserved 0xd5 flt_raw_7 7 r 0 ts2 voltage is above programmed voltage. 0xd5 flt_raw_6 6 r 0 ts1 voltage is above programmed voltage. 0xd5 flt_raw_5 5 r 0 1 when die temperature is greater than tdie_shutdown. 0xd5 flt_raw_4 4 r 0 reserved 0xd5 flt_raw_3 3 r 0 reserved
p9027lp - r datasheet ? 2016 integrated device technology, inc 20 april 28, 2016 0xd5 flt_raw_2 2 r 0 1 when end of charge (eoc) pin is set. 0xd5 flt_raw_1 1 r 0 reserved 0xd5 flt_raw_0 0 r 0 1 when enable ( en ? ? ? ? ) pin is set high. enabled fault flag. if the fault conditi on exist s and this fault is enabled in masked f ault enable register, the bit for the fault in flt_mskd will be set. table 14 . masked fault condition byte address byte name bit field typical default value description 0xd6 flt_mskd 7 :5 r 0 reserved. 0xd6 flt_mskd 4 r 0 reserved. 0xd6 flt_mskd 3:0 r 0 reserved 0xd 7 flt_mskd 7 r 0 ts2 voltage is above programmed voltage. end of power transfer packet sent ( 0x0 3) if triggered . 0xd 7 flt_mskd 6 r 0 ts1 voltage is above programmed volt age. end of power transfer packet sent ( 0x0 3) if triggered . 0xd 7 flt_mskd 5 r 0 1 when die temperature is greater than tdie_shut d own . end of power transfer packet sent ( 0x0 2 ) if triggered . 0xd 7 flt_mskd 4 r 0 reserved 0xd 7 flt_mskd 3 r 0 reserved 0xd 7 flt_mskd 2 r 0 1 when end o f charge (eoc) pin is set. end of power transfer packet sent ( 0x0 1 ) if triggered . 0xd 7 flt_mskd 1 r 0 reserved 0xd 7 flt_mskd 0 r 0 1 when enable ( en ? ? ? ? ) pin is set high. end of power transfer packet sent ( 0x0 2 ) if triggere d . enabled fault flag. if the fault condition exists and this fault is enabled in masked interrupt enable register, the bit for the fault in intr _mskd will be set. table 15 . masked interrupt register byte address byte name bit fie ld typical default value description 0xd8 intr_mskd 7:5 r 0 reserved. 0xd8 intr_mskd 4 r 0 reserved. 0xd8 intr_mskd 3:0 r 0 reserved 0xd9 intr_mskd 7 r 0 ts2 voltage is above programmed voltage, int pin will be toggled.
p9027lp - r datasheet ? 2016 integrated device technology, inc 21 april 28, 2016 byte address byte name bit fie ld typical default value description 0xd9 intr_mskd 6 r 0 ts1 volt age is above programmed voltage, int pin will be toggled. 0xd9 intr_mskd 5 r 0 1 when die temperature is greater than tdie_shut d own, int pin will be toggled. 0xd9 intr_mskd 4:3 r 0 reserved 0xd9 intr_mskd 2 r 0 1 when end of charge (eoc) pin is set int ? ? ? ? ? pin will be toggled. 0xd9 intr_mskd 1 r 0 reserved 0xd9 intr_mskd 0 r 0 1 when enable ( en ? ? ? ? ) pin is set high, int ? ? ? ? ? pin will be toggled. setting 1s in the register enable co - responding fault to send end of power transfer . table 16 . masked fault enable register byte address byte name bit field typ ical default value description 0x00 flt_mskd_en 7:5 r/w 0 reserved. 0x00 flt_mskd_en 4 r/w 0 thermal regulation loop is fault ena bled send end of power packet. 0x00 flt_mskd_e n 3:0 r/w 1 reserved . 0x01 flt_mskd_en 7 r/w 1 ts2 fault is enabled to send end of power packet. 0x01 flt_mskd_en 6 r/w 1 ts1 fault is enabled to send end of power packet. 0x01 flt_mskd_en 5 r/w 1 die temperature shutdown is enabled to send end of pow er packet. 0x01 flt_mskd_en 4:3 r/w 1 reserved . 0x01 flt_mskd_en 2 r/w 1 end of charge is enabled to send end of power packet. 0x01 flt_mskd_en 1 r/w 1 reserved . 0x01 flt_mskd_en 0 r/w 1 function to use en pin to send end of power transfer is enabled . setting 1s in the register enable co - responding fault to pull high int ? ? ? ? ? pin. table 17 . masked interrupt enable byte address byte name bit field typical default value description 0x02 intr_mskd_en 7:5 r/w 1 reserved. 0x02 intr_mskd_en 4 r/w 1 thermal regulation interrupt is enabled to toggle int ? ? ? ? ? pin .
p9027lp - r datasheet ? 2016 integrated device technology, inc 22 april 28, 2016 byte address byte name bit field typical default value description 0x02 intr_mskd_en 3:0 r/w 1 reserved . 0x0 3 intr_mskd_en 7 r /w 1 ts2 interrupt is enabled to toggle int ? ? ? ? ? pin . 0x0 3 intr_mskd_en 6 r /w 1 ts1 interrupt is enabled to toggle int ? ? ? ? ? pin . 0x0 3 intr_mskd_en 5 r /w 1 die temperature in terrupt is enabled to toggle int ? ? ? ? ? pin . 0x0 3 intr_mskd_en 4:3 r /w 1 reserved . 0x0 3 intr_mskd_en 2 r /w 1 end of charge int errupt is enabled to toggle int ? ? ? ? ? pin . 0x0 3 intr_mskd_en 1 r /w 1 reserved . 0x0 3 intr_mskd_en 0 r /w 1 functio n to use en pin to pull high int ? ? ? ? ? pin is enabled. when tdie >= tdie _ shdn _ off + tdie_shdn_hys , 9027lp - r will shut down. when tdie < tdie_shdn_off, die tempera ture shutdown function is off; however 9027lp - r may send ept to shut down p 9235 a - r. if tdie _ shdn _ off > tdie > tdie _ shdn _ off - 10c , 9027lp - r will send ept because of die temperature. if tdie < tdie _ shdn _ off - 20c , no ept will be sent because of die temperature . table 18 . die temperature shutdown register byte address byte name bit field typical default value description 0x0 8 tdie_ shdn _ off 7 r/w 0 die temperature shutdown select. 0 : die temperature shutdown off 1 : 130 0 c 2 : 14 0 0 c 3 : 150 0 c 0x0 8 tdie_ shdn _ off 6 r/w 1 0x0 8 tdie _shdn_hys 5 r/w 1 die temperature shutdown hysteresis select (thermal control start temperature = hysteresis + thermal control off temperature) 0 : 10 0 c 1 : 20 0 c 0x0 8 intr_mskd_en 4:0 r/w 0 reserved.
p9027lp - r datasheet ? 2016 integrated device technology, inc 23 april 28, 2016 table 19 . output volta ge setting (vset) byte address byte name bit field typical default value description 0x 33 vset_en 7 r/w 0 vset (out voltage) set enable 0 : out voltage set was disabled, vset will be set from external resistance on vset pad . 1: out voltage set was ena bled, vset_value will be used for out voltage. 0x 33 reserved 6:5 - - reserved. 0x 33 vset_value 4:0 r/w 0 0 : out voltage value = 5.00 v 1:5 : reserved 6 : out voltage value = 4.50 v 7, 8 : out voltage value = 4.75 v 9, 10 : out voltage value = 5.25 v 11, 12 : out voltage value = 5.50 v 13, 14 : out voltage value = 5.75 v 15, 16, 17 : out voltage value = 6.00 v to have correct temperature information from adc_ts1 and/or adc_ts2, the correct valu e sensing resistor needs to be connected onto ts1 to gnd and/or ts2 to gnd. table 20 . thermistor ts1 and ts2 register adc reading address register name r/w default function and description 0x69 [7:0] ts1 [7:0] r - ts1 (external tem perature sensor1) value read (0 ~ 255) 0x6b[7:0] ts2 [7:0] r - ts2 (external temperature sensor2) value read (0 ~ 255) table 21 . operating frequency register adc reading byte address byte name bit field typical default value desc ription 0x 7 e reserved 7:4 x x reserved . 0x7 e lx_fsw 3:0 r - o perating frequency = 1 / (lx_ fsw * 3.125 ns) 0x 7 f lx_fsw 7:0 r - o perating frequency = 1 / (lx_ fsw * 3.125 ns)
p9027lp - r datasheet ? 2016 integrated device technology, inc 24 april 28, 2016 table 22 . communication packet register adc readin g byte address byte name bit field typical default value description 0x 81 ept 7:0 r 1 end of power transfer packet parameter value read : 01: charge complete . 02: internal fault . 03: over temperature . 05: over current. ff: no fault . 0x 82 reserved 7:0 - - reserved. 0x 83 sigstr 7:0 r - signal strength packet parameter value read . 0x 84 reserved 7:0 - - reserved. 0x 85 ctrlerr 7 r - control error packet parameter value read . 0x 86 reserved 7:0 - - reserved. 0x 87 chgsts 7:0 r 1 charge status packet parame ter value read . 0x 88 reserved 7:4 - - reserved. 0x 88 rcvdpwr 4:0 r - received power packet parameter value read (12 - bit) : 2.44 mw unit @5w system . normally only msb 8 - bits [11:4] are used for this parameter: 39.04 mw unit . 0x 89 rcvdpwr 7:0 r -
p9027lp - r datasheet ? 2016 integrated device technology, inc 25 april 28, 2016 pac kage information figure 12 . wlcsp landing pattern (awg40)
p9027lp - r datasheet ? 2016 integrated device technology, inc 26 april 28, 2016 figure 13 . wlcsp package outline drawing (awg40)
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